Adaptive online filter for dc offset elimination

ABSTRACT

A phase angle detector with a PLL, a power converter, and a method for reducing offsets in an input signal, in which an adaptive offset processor selectively removes a DC offset component from the input signal to generate a modified signal including a fundamental frequency component and higher order harmonics of the input signal with the DC offset component removed, and the PLL provides a phase angle signal at least partially according to the modified signal.

REFERENCE TO RELATED APPLICATION

This application is a divisional of, and claims priority to and thebenefit of, U.S. patent application Ser. No. 13/537,993, filed on Jun.29, 2012, entitled ADAPTIVE ONLINE FILTER FOR DC OFFSET ELIMINATION, theentirety of which application is hereby incorporated by reference.

BACKGROUND

Motor drives and other power conversion systems typically receive ACinput power from a grid or other power source and convert that to DC fordriving a load such as a DC motor, or an inverter may convert the DC toAC output power for driving an AC motor or other load. Many such powerconverters include active front end (AFE) rectifier stages withswitching devices to rectify the input AC power. In many powerconversion control schemes, synchronization of the front end converteroperation with the phase angle of the input AC power is desirable, forinstance, in performing power factor control, attempting to minimizetotal harmonic distortion, etc. Synchronizing power converters to thegrid power is typically done using phase locked loops (PLLs) to providea phase signal to the converter controller based on sensed phasevoltages. However, many phase voltage sensors suffer from low frequencyor DC offsets or drift, as well as higher order harmonics, and imbalancein the voltage which can corrupt the phase signal output from the phaselock loop.

Some solutions to this problem employ one or more tracking filters inthe feedback loop of a PLL to eliminate error signal disturbances.Examples are illustrated and described in U.S. patent application Ser.No. 12/627,472 to Kerkman et al., filed Nov. 30, 2009, published on Jun.2, 2011 as Publication No. US 2011/0128054 A1 entitled “PHASE LOCK LOOPWITH TRACKING FILTER FOR SYNCHRONIZING AN ELECTRIC GRID”, and assignedto the assignee of the present disclosure, which is hereby incorporatedby reference in its entirety. However, difficulties may arise inimplementing harmonic tracking filters in conjunction with a trackingfilter at the fundamental frequency due to filter bandwidth overlap orproximity, and this approach may thus yield bandwidth limitations forthe PLL.

U.S. patent application Ser. No. 12/706,488 to Kerkman et al., filedFeb. 16, 2010, published on Aug. 18, 2011 as Publication No. US2011/0199072 A1 entitled “POWER CONTROL SYSTEM AND METHOD”, and assignedto the assignee of the present disclosure provides electrical devicecontrol systems and methods using tracking filter devices, and U.S.patent application Ser. No. 12/627,400 to Seibel et al., filed Nov. 30,2009, published on Jun. 2, 2011 as Publication No. US 2011/0130993 A1entitled “DIGITAL IMPLEMENTATION OF A TRACKING FILTER”, and assigned tothe assignee of the present disclosure presents a digital implementationof such a tracking filter. The entireties of these publishedapplications are hereby incorporated by reference. Other solutions tothe above shortcomings may include low pass filter nulling of the DCoffset, but this requires additional hardware thereby increasing thecost, size and weight of power converter systems.

Accordingly, there is a continuing need for improved techniques andapparatus for controlling offsets in grid synchronization PLLs and inother applications in which offsets need to be removed from an inputsignal.

SUMMARY

Various aspects of the present disclosure are now summarized tofacilitate a basic understanding of the disclosure, wherein this summaryis not an extensive overview of the disclosure, and is intended neitherto identify certain elements of the disclosure, nor to delineate thescope thereof. Rather, the primary purpose of this summary is to presentvarious concepts of the disclosure in a simplified form prior to themore detailed description that is presented hereinafter. The presentdisclosure provides adaptive online filtering techniques by whichoffsets can be removed from one or more input signals prior to use in aPLL feedback path, thereby facilitating offset signal control with thepossibility of using one or more tracking filters to control higherorder harmonics while avoiding or mitigating the potential of filteroverlap in a PLL augmented with one or more tracking filters. Thetechniques and apparatus of the present disclosure find utility in powerconverter synchronization situations as well as in other applications inwhich it is desired to remove DC offsets from one or more input signals.

Adaptive offset processing apparatus is disclosed which includes anadaptive tracking filter with a passband corresponding to a frequencysignal, such as a frequency signal of a phase lock loop, along with alow pass filter. The adaptive tracking filter removes frequencycomponents of an input signal that are outside the passband to provide afundamental frequency signal that is subtracted from the input signal togenerate a first modified signal with the fundamental frequencycomponent substantially removed. This signal as provided to the low passfilter which generates a second modified signal including a DC offsetcomponent with a fundamental and higher order harmonics substantiallyremoved. The second modified signal is subtracted from the input signalto generate a third modified signal substantially including thefundamental and higher order harmonics with the DC offset componentsubstantially removed. In certain embodiments, the low pass filtercutoff frequency is below the fundamental frequency component, and theapparatus may be implemented to accommodate analog and/or digital inputas well as analog and/or digital frequency signals.

In accordance with further aspects of the disclosure, a phase angledetector apparatus is provided, which includes an adaptive offsetprocessing apparatus operative to selectively remove a DC offsetcomponent from an input signal. The adaptive offset processing apparatusprovides a modified output signal substantially including thefundamental frequency component and higher order harmonics of the inputsignal, with the DC offset component substantially removed. The phaseangle detector apparatus further includes a phase lock loop to provide aphase angle output signal at least partially according to the modifiedoutput signal from the adaptive offset processor. In certainembodiments, the phase angle detector includes one or more trackingfilters coupled with the phase lock loop to estimate and reduce adisturbance frequency component in the modified signal.

A power conversion system is provided in accordance with other aspectsof the disclosure for converting power from an AC power source to drivea load. The power conversion system includes an active front end (AFE)converter, such as a switching rectifier in certain embodiments, whichconverts input power to output DC power, and a converter controllerprovides one or more switching control signals to the active front endconverter. The power conversion system also includes a phase angledetector that receives one or more sensor input signals representing ACpower source phase voltages, and provides a phase angle signal to theconverter controller for synchronizing with the AC power source. Thephase angle detector includes an adaptive offset processor whichselectively removes a DC offset component from the sensor inputsignal(s) to generate at least one modified signal substantiallyincluding the fundamental frequency component and higher order harmonicsof the sensor input signal with the DC offset component substantiallyremoved. In addition, the phase angle detector includes a phase lockloop which provides the phase angle signal to the converter based atleast partially on the modified signal from the adaptive offsetprocessor. In certain embodiments, one or more tracking filters areoperatively coupled in the phase lock loop to estimate and reduce adisturbance frequency component in the modified signal.

In accordance with further aspects of the present disclosure, a methodand a non-transitory computer readable medium with computer executableinstructions are provided for reducing at least one offset component inan input signal. The method includes removing substantially allfrequency components of the input signal that are outside an adaptivepassband defined by a frequent signal to generate a fundamentalfrequency signal, as well as subtracting the fundamental frequencysignal from the input signal to generate a first modified signal with afundamental frequency component substantially removed. The methodfurther includes removing substantially all high frequency componentsabove a cutoff frequency from the first modified signal to generate asecond modified signal including a DC offset component with thefundamental frequency component and higher order harmonics substantiallyremoved. The method also include subtracting the second modified signalfrom the input signal to generate a third modified signal substantiallyincluding the fundamental frequency component and higher order harmonicsof the input signal with the DC offset component substantially removed.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description and drawings set forth certain illustrativeimplementations of the disclosure in detail, which are indicative ofseveral exemplary ways in which the various principles of the disclosuremay be carried out. The illustrated examples, however, are notexhaustive of the many possible embodiments of the disclosure. Otherobjects, advantages and novel features of the disclosure will be setforth in the following detailed description when considered inconjunction with the drawings, in which:

FIG. 1 is a schematic diagram illustrating an exemplary adaptive offsetprocessor for selective removal of an offset from an input signal inaccordance with one or more aspects of the present disclosure;

FIG. 2 is a schematic diagram illustrating an exemplary phase angledetector including an adaptive offset processor operating on inputsensor signals in providing modified signals with offsets removed to aphase lock loop in accordance with further aspects of the disclosure;

FIG. 3 is a flow diagram illustrating an exemplary method for reducingor removing offset or drift from one or more input signals in accordancewith further aspects of the disclosure; and

FIG. 4 is a schematic diagram illustrating an exemplary power conversionapparatus with a phase angle detector and adaptive offset processor inaccordance with other aspects of the disclosure.

DETAILED DESCRIPTION

Referring now to the figures, several embodiments or implementations arehereinafter described in conjunction with the drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the various features are not necessarily drawn to scale.

An adaptive offset processing apparatus 100 is illustrated in FIG. 1,which may be used in any application in which it is desirable to removean offset from an input signal. For example, the apparatus 100 may beused in a phase angle detector 10 as illustrated and described below inconnection with FIG. 2, and such may be employed in power conversionsystems as exemplified in FIG. 4, although the present disclosure is notlimited to power conversion or grid phase synchronization applications.The adaptive offset processor 100 and the components 110, 120, 130and/or 140 thereof may be implemented in hardware (including analog ordigital circuitry or combinations thereof), processor-executed softwareor firmware, programmable logic, and/or combinations thereof. In motordrive or other power converter applications, for instance, the adaptiveoffset processing concepts of the present disclosure may be implementedas firmware upgrades to a processor-based power converter controller(e.g., FIG. 4), without the added cost and weight of additional hardwarefiltering in order to mitigate or eliminate offsets or drift problemsoften associated with phase voltage sensors used in synchronizing powerconversion equipment with a power grid.

The adaptive offset processing apparatus 100 operates on one or moreinput signals received at an input 102. In the example of FIG. 1, asingle phase voltage sensor input signal Va is shown, and in othertypical applications the adaptive offset processing apparatus 100 may bereplicated for any number of such phase voltage sensor input signals(e.g., Va, Vb and Vc in a typical three-phase case, such as shown inFIGS. 2 and 4 below). As seen in the example of FIG. 3, moreover, theinput signal may be received from a sensor 2, such as a phase voltagesensor conventionally found in power conversion system such as motordrives. In other possible implementations, the input signal(s) may beobtained from any form of sensor(s) 2, including without limitationcurrent sensors. In this regard, sensor drift presents difficulties withrespect to phase synchronization, and is manifest as DC offsets in thesignals provided by the sensors 2, particularly for conventional voltagesensors. This drift or offset in the sensor signal, in turn, has adverseeffects on the ability to create a phase output signal (e.g., Θ providedas a PLL output 29 as seen in FIG. 2 below) using the closed loopprocessing of a phase lock loop. In order to facilitate reduction orelimination of such DC offsets or drifts in one or more sensor inputsignals, the offset processing apparatus 100 in FIG. 1 includes anadaptive tracking filter 110 receiving the input signal Va via a sensorsignal input 102 and the tracking filter 110 also receives a frequencysignal ω_(e) via a second input 104. The apparatus 100 also includes afirst summer 120, a low pass filter 130, and a second summer 140providing a modified (e.g., offset removed) output signal 142 to anoutput 106. Moreover, unlike prior offset reduction approaches usingfundamental frequency tracking filters within the feedback path of aphase lock loop, the adaptive tracking filter 110 of the presentdisclosure operates directly on the sensor input signal Va and providesat least one modified output signal 142 which can then be introducedinto a PLL as shown in FIG. 2 below. In this manner, the offsetreduction/elimination achieved by the offset processor 100 is notimpacted by overlap or proximity of harmonic tracking filters 30 (e.g.,FIG. 2 below) operating on the feedback path of the PLL, and theoperation of the offset processor 100 does not adversely impact theoperation of such harmonic tracking filters 30.

The adaptive tracking filter 110 in certain embodiments is a bandpassfilter including an adaptive passband which is defined by the frequencysignal ω_(e). In operation, the tracking filter 110 performs bandpassfiltering to remove substantially all frequency components of the inputsignal Va that lie outside the adaptive passband while passing thefrequencies within the passband. Accordingly, the adaptive filter 110generates a fundamental frequency signal 112 that is provided as asubtractive input to the first summer 120. In this regard, as is knownwith analog and/or digital filtering technology, an ideal bandpassfilter would remove all frequency components outside a defined passband,but in practice, analog and digital filters are not perfect.Accordingly, it will be appreciated that the adaptive tracking filter110 may pass reduced levels of certain frequency components outside itsdefined passband, but these are at least substantially reduced comparedwith the corresponding output-of-band components of the original inputsignal Va.

In addition, the bandpass filter implemented by certain embodiments ofthe adaptive tracking filter 110 is “adaptive” as the passband isdefined by the frequency signal ω_(e) received via the second input 104.In practice, this frequency signal ω_(e) can be a frequency estimateprovided by a phase lock loop (e.g., see FIG. 2), or can be receivedfrom any other suitable frequency selection component of a given signalprocessing system. The adaptive tracking filter 110, whether implementedas analog circuitry or as a digital filter, adapts the passbandaccording to the received frequency signal ω_(e), and thus the filter110 itself, and the offset processor 100 as a whole, adapt to thereceived frequency signal ω_(e). In certain embodiments, the adaptivetracking filter 110 may be implemented as a digital tracking filteraccording to the concepts disclosed in US patent application publicationnumber US 2011/0130993 A1, assigned to the Assignee of the presentdisclosure, which is incorporated herein by reference in its entirety.

The initial summer 120 subtracts the fundamental frequency signal 112from the input signal Va and thereby generates a first modified signal122 with the fundamental frequency component substantially removed. Inpractice, the summer 120 (as well as the final summer 140 in FIG. 1) canbe implemented as analog summing circuitry with various operationalamplifiers, resistors, and other suitable components, or the summationfunction of the summing components 120, 140 may be implemented inprocessor-executed software, firmware, programmable logic, etc., fordigital filtering and signal processing of sampled digital valuesrepresenting the various signals 112, 122, 132 and 142 described herein.In this regard, the sensor input signal(s) (e.g., Va in FIG. 1) and/orthe frequency signal ω_(e) can be analog signals or one or both of thesemay be a digital signal including a plurality of values or samples.

The low pass filter (LPF) 130 receives the first modified signal 122from the summer 120 and implements low pass filtering according to anassociated cutoff frequency. In certain embodiments, the cutofffrequency of the low pass filter 130 is below the fundamental frequencycomponent of the input signal Va (e.g., below the frequency representedby the frequency signal co, such as about 1 Hz to 10 Hz in certainembodiments). In certain implementations, moreover, the low pass filter130 may be adaptive as well, with the associated cutoff frequency beingadjustable according to the frequency signal ω_(e) received from theinput 104. The low pass filtering removes substantially all the highfrequency components from the first modified signal 122 and the filter130 generates a second modified signal 132 which includes the DC offsetcomponent of the original input signal Va, without the fundamentalfrequency component and without the higher order harmonics. In thisregard, as discussed above in connection with the tracking filter 110,an ideal low pass filter 130 would remove all such fundamental andhigher order harmonic components, but in practice the low pass filter130 may be implemented so as to substantially remove such frequencycomponents, with certain frequencies above the established cutofffrequency possibly being included, but substantially reduced.

The second modified signal 132 from the low pass filter 130 is providedas a subtractive input to the second summer 140 which subtracts thissignal 132 from the sensor input signal Va, and the resulting thirdmodified signal 142 is provided to the output 106 substantiallyincluding the fundamental frequency component and higher order harmonicsof the input signal Va with the DC offset component thereofsubstantially removed. As a result of the operation of the adaptiveoffset processor 100, therefore, the modified signal Va′ provided at theoutput 106 is substantially the same as the sensor input signal Va,except that the DC or very low frequency offsets are removed.Consequently, any sensor drift or other source of DC offset in thesignal path providing the input Va is effectively removed by the offsetprocessing apparatus 100.

FIG. 2 illustrates an exemplary phase angle detector apparatus 10including a three phase adaptive offset processor or processors 100, forwhich the processing of each associated phase voltage sensor inputsignal Va, Vb, Vc generally operates as described above in connectionwith FIG. 1. In certain implementations, three separate adaptive officeset processors 100 can be provided, each operating on an associatedphase voltage sensor input signal 102 Va, Vb, Vc from the phase voltagesensors 2, and each generating a corresponding modified signal 142 Va′,Vb′, Vc′ with any DC offset or drift removed therefrom. In otherpossible embodiments, single adaptive offset processor 100 can be usedwhich accommodates multiple input signals 102 and provides multiplecorresponding modified output signals 142 at the output 106. The offsetprocessor(s) 100, moreover, is/are adaptive as described above,receiving a frequency input signal ω_(e) via an input 104, where theprocessor(s) 100 may operate according to a single frequency inputsignal ω_(e) or a separate frequency signal ω_(e) can be provided foreach phase. In certain embodiments where the offset processor(s) 100 isimplemented in a power conversion system controller (e.g., convertercontroller 330 shown in FIG. 4 below), digital signal processing can beused for implementing the adaptive offset processing system or systems100 via processor-executed software or firmware with the necessarysignal conditioning circuitry (e.g., analog-to-digital converters forproviding digital values representing signals from the sensors 2).

As seen in FIG. 2, the offset-reduced modified signals 142 Va′, Vb′, Vc′are provided as inputs to a stationary-to-synchronous converter 27 of aphase lock loop 20 which implements a stationary referenceframe-to-synchronous reference frame conversion for generation of thePLL phase output signal Θ. This is indicated in FIG. 2 as atransformation of a three dimensional stationary reference frame vectorKV′_(abc) based on the signal inputs 142 (Va′, Vb′, Vc′) from theadaptive offset processor 100 to provide a synchronous reference frameset of values including a q-axis voltage Vq′, a d-axis voltage Vd′, anda zero sequence value represented as a vector V′_(qd0). The phase lockloop 20 receives a synchronous reference frame d-axis voltage commandVd* (e.g., from a converter controller 330 as shown in FIG. 4 below),and a first summer 21 subtracts a d-axis signal Vd from the d-axisvoltage command Vd* to generate an error signal. In practice,synchronous reference frame power converter control of an active frontend rectifier (e.g., in a motor drive grid voltage synchronizationimplementation) will generally have the d-axis voltage command Vd* setto zero, with the q-axis voltage being controlled according to outputmotor load speed and/or torque requirements, although a zero valued-axis voltage command Vd* is not a requirement of all embodiments ofthe present disclosure.

The error signal from the summer 21 as provided to a compensatorimplemented as an integrator 22 (K_(i)/s) and an amplifier 23 (K_(p))with the outputs of the integrator 22 and the amplifier 23 being addedby a summer 24. The output of the summer 24 may be supplemented oroffset by a frequency signal ω_(ff) using a summer 25, the output ofwhich is the PLL frequency estimate signal ω_(e) that is provided as aninput to the adaptive offset processor 100. In addition, the frequencyestimate signal ω_(e) is integrated by an integrator 26 (1/s) togenerate the output phase signal Θ provided to the PLL output 29 andalso used as an input by the stationary-to-synchronous converter 27. The3-2 reference frame converter 27 provides the d-axis voltage referencesignal Vd′ (with DC or low frequency offsets or drift removed byoperation of the adaptive offset processor(s) 100) either directly as asubtractive input to the summer 21 to complete the PLL feedback loop, orone or more harmonic tracking filters 30 can be provided along with anadditional summer 28 in certain embodiments. Although the embodiment ofFIG. 2 is illustrated as using a stationary-synchronous reference frameconversion 27 to operate on d-axis voltage signals, alternateembodiments are possible using sine and cosine processing as illustratedand described for example in US patent application publication number US2011/0130993 A1, incorporated herein by reference.

As seen in FIG. 2, in-loop harmonic tracking filter embodiments can beimplemented using one or more tracking filters 30, each receiving thefrequency estimate signal ω_(e) and the modified d-axis voltage signalVd′ as inputs. As disclosed in US patent application publication numbersUS 2011/0130993 A1 and US 2011/0199072 A1, the tracking filters 30 canbe adapted to remove selected harmonics based on the frequency estimatesignal ω_(e), for instance, with one of the filters 30 set to remove thesecond harmonic, in combination with one or more further trackingfilters 30 set to other higher (e.g., N^(TH)) order harmonics. Inoperation, the tracking filters 30 provide filtered outputs assubtractive inputs to the summer 28 for offsetting the Vd′ signal fromthe 3-2 converter 27 to provide the subtractive input to the initialsummer 21. In this regard, previous attempts to combine such harmonicremoval in the PLL loop with an in-loop tracking filter set to thefundamental (N=1) to control drift or offset suffered from filterbandwidth overlap or close filter band proximity. The implementation ofFIG. 2, on the other hand, advantageously performs the offsetremoval/mitigation prior to introducing the sensor signals into the PLLloop, whereby such filter overlap is not an issue, and voltage sensordrift can be addressed without compromising the harmonic removalcapabilities of the PLL/tracking filter architecture.

FIG. 3 provides a flow diagram 200 illustrating an exemplary process forreducing offset associated with one or more input signals in accordancewith further aspects of the present disclosure. While the method 200 isillustrated and described below in the form of a series of acts orevents, it will be appreciated that the various methods of the presentdisclosure are not limited by the illustrated ordering of such acts orevents. In this regard, except as specifically provided hereinafter,some acts or events may occur in different order and/or concurrentlywith other acts or events apart from those illustrated and describedherein. In addition, not all illustrated steps may be required toimplement a process or method in accordance with the present disclosure,and one or more such acts may be combined. Furthermore, the illustratedmethods may be implemented in hardware, processor-executed software, orcombinations thereof, in order to provide the adaptive offset filteringfunctionality described herein, and may be employed in any signalprocessing including without limitation power converters and associatedapparatus. For instance, the adaptive offset processing apparatus 100illustrated and described above may implement the method 200 in certainembodiments.

At 202 in FIG. 3, one or more sensor input signals are received (e.g.,Va, Vb, Vc received at an adaptive offset processor input 102), and afrequency signal (e.g., ω_(e)) is received at 204. At 206, the sensorinput signal(s) is filtered using an adaptive tracking filter (e.g.,filter 110 in FIG. 1) having a center frequency set by the frequencysignal (ω_(e)) in order to generate a fundamental frequency signal(e.g., signal 112 above). At 208 in FIG. 3, the fundamental frequencysignal is subtracted from the sensor input signal (summer 120 in FIG. 1)to generate a first modified signal with the fundamental frequencycomponent removed (signal 122). At 210, the first modified signal isfiltered (low pass filter 130 in FIG. 1) to generate a second modifiedsignal (132) including the DC offset component with a fundamental andhigher order harmonics removed. At 212, the second modified signal issubtracted from the sensor input signal (summer 140) to generate a thirdmodified signal (Va′ 142 in FIG. 1, Va′, Vb′ & Vc′ in FIG. 2) with theDC offset component removed. This signal 142 is then provided to one ormore tracking filters at 214 in certain embodiments (e.g. trackingfilters 30 in FIG. 2) for harmonic reduction in the phase lock loop.This process 200 may then repeat steps 202-214 for further iterations incontinuous fashion. In accordance with further aspects of the presentdisclosure, moreover, a non-transitory computer readable medium isprovided, such as a computer memory, a memory within a power convertercontrol system (e.g., switch control system 330 in FIG. 4 below), aCD-ROM, floppy disk, flash drive, database, server, computer, etc. whichhas computer executable instructions for performing the processesdescribed above.

FIG. 4 illustrates an embodiment of a power conversion system 300receiving multiphase AC input power from a power grid 302 and providingoutput AC power (e.g., variable frequency, variable amplitude) to a load304. The load 304 may, but need not be, an AC motor. The power converter300 includes an active front end rectifier 310 including a plurality ofswitching devices (not shown) for selectively connecting an associatedone of the AC input phases with an upper or lower DC link connection,where the switching devices of the active front end 310 are operatedaccording to switching control signals from a converter controller 330.The converter controller 330 may be implemented as any suitablehardware, processor-executed software, programmable logic, etc., orcombinations thereof. Certain embodiments may be AC-DC power converters,in which case the resulting converted DC output of the active front end310 is provided directly to drive a load. In other embodiments (as shownin FIG. 4), one or more subsequent power conversion stages may beprovided. In the illustrated example, an inverter 320 receives DC inputpower from the intermediate DC link and converts this to variablefrequency AC output power to drive the load 304, where the inverter isalso operated according to switching control signals from the convertercontroller 330. The system 300 includes one or more sensors 2 formeasuring or detecting the AC input phase voltages of the power grid302, and the sensor output signals are provided as inputs 102 to anadaptive offset processor 100 similar to that described above inconnection with FIGS. 1-3. The adaptive offset processor 100 is part ofa phase angle detector 10 (FIG. 2 above) which receives a d-axis voltagecommand input Vd* from the converter controller 330, and the angledetector 10 provides a phase angle output 0 to the controller 330 forsynchronizing the operation of the active front end 320 to the phase ofthe power grid 302. In certain embodiments, the phase angle detector 10may be integrated within the converter controller 330, or the angledetector 10 may be separately implemented.

The above examples are merely illustrative of several possibleembodiments of various aspects of the present disclosure, whereinequivalent alterations and/or modifications will occur to others skilledin the art upon reading and understanding this specification and theannexed drawings. In particular regard to the various functionsperformed by the above described components (assemblies, devices,systems, circuits, and the like), the terms (including a reference to a“means”) used to describe such components are intended to correspond,unless otherwise indicated, to any component, such as hardware,processor-executed software, or combinations thereof, which performs thespecified function of the described component (i.e., that isfunctionally equivalent), even though not structurally equivalent to thedisclosed structure which performs the function in the illustratedimplementations of the disclosure. In addition, although a particularfeature of the disclosure may have been disclosed with respect to onlyone of several implementations, such feature may be combined with one ormore other features of the other implementations as may be desired andadvantageous for any given or particular application. Also, to theextent that the terms “including”, “includes”, “having”, “has”, “with”,or variants thereof are used in the detailed description and/or in theclaims, such terms are intended to be inclusive in a manner similar tothe term “comprising”.

The following is claimed:
 1. A method for reducing at least one offsetcomponent in an input signal, the method comprising: using an adaptivetracking filter having an adaptive passband defined by a frequencysignal, removing substantially all frequency components of the inputsignal that are outside the passband to generate a fundamental frequencysignal; subtracting the fundamental frequency signal from the inputsignal to generate a first modified signal with a fundamental frequencycomponent substantially removed; using a low pass filter having a cutofffrequency, removing substantially all high frequency components abovethe cutoff frequency from the first modified signal to generate a secondmodified signal including a DC offset component with the fundamentalfrequency component and higher order harmonics substantially removed;and subtracting the second modified signal from the input signal togenerate a third modified signal substantially including the fundamentalfrequency component and higher order harmonics of the input signal withthe DC offset component substantially removed.
 2. The method of claim 1,wherein the cutoff frequency of the low pass filter is below thefundamental frequency component.
 3. The method of claim 1, wherein atleast one of the input signal and the frequency signal is an analogsignal.
 4. The method of claim 1, wherein at least one of the inputsignal and the frequency signal is a digital signal including aplurality of values.
 5. The method of claim 1, wherein the cutofffrequency of the low pass filter is above the fundamental frequencycomponent.
 6. The method of claim 1, comprising estimating and reducinga disturbance frequency component in the third modified signal.
 7. Themethod of claim 6, comprising estimating and reducing the disturbancefrequency component in the third modified signal using at least onetracking filter.
 8. The method of claim 6, wherein the cutoff frequencyof the low pass filter is below the fundamental frequency component. 9.The method of claim 6, wherein at least one of the input signal and thefrequency signal is an analog signal.
 10. The method of claim 6, whereinat least one of the input signal and the frequency signal is a digitalsignal including a plurality of values.
 11. The method of claim 6,wherein the cutoff frequency of the low pass filter is above thefundamental frequency component.
 12. A non-transitory computer readablemedium comprising computer executable instructions for reducing at leastone offset component in an input signal, the computer readable mediumcomprising computer executable instructions for: removing substantiallyall frequency components of the input signal that are outside anadaptive passband defined by a frequency signal to generate afundamental frequency signal; subtracting the fundamental frequencysignal from the input signal to generate a first modified signal with afundamental frequency component substantially removed; removingsubstantially all high frequency components above a cutoff frequencyfrom the first modified signal to generate a second modified signalincluding a DC offset component with the fundamental frequency componentand higher order harmonics substantially removed; and subtracting thesecond modified signal from the input signal to generate a thirdmodified signal substantially including the fundamental frequencycomponent and higher order harmonics of the input signal with the DCoffset component substantially removed.
 13. The computer readable mediumof claim 12, wherein the cutoff frequency of the low pass filter isbelow the fundamental frequency component.
 14. The computer readablemedium of claim 12, wherein at least one of the input signal and thefrequency signal is an analog signal.
 15. The computer readable mediumof claim 12, wherein at least one of the input signal and the frequencysignal is a digital signal including a plurality of values.
 16. Thecomputer readable medium of claim 12, wherein the cutoff frequency ofthe low pass filter is above the fundamental frequency component. 17.The computer readable medium of claim 12, comprising computer executableinstructions for estimating and reducing a disturbance frequencycomponent in the third modified signal.
 18. The computer readable mediumof claim 17, comprising computer executable instructions for estimatingand reducing the disturbance frequency component in the third modifiedsignal using at least one tracking filter.
 19. The computer readablemedium of claim 17, wherein the cutoff frequency of the low pass filteris below the fundamental frequency component.
 20. The computer readablemedium of claim 17, wherein at least one of the input signal and thefrequency signal is an analog signal.